-Error Handling

9.11 Secondary Cache Error Protection and Handling

Error Handling

This section describes error handling for the data array and the tag array. As shown in Table 9-4, errors are not detected for the way prediction table.

Data Array

The 128-bit wide secondary cache data array is protected by a 9-bit wide ECC. An even parity bit is used for rapid detection of correctable (single-bit) errors; when a correctable parity error is detected, the data is sent through the data corrector. The parity bit does not have any logical effect on the processor's ability to either detect or correct errors.

Whenever the processor writes the secondary cache data array, it drives the proper ECC on SCDataChk(8:0) and even parity on SCDataChk(9).

Data Array in Correction Mode

The secondary cache operates in correction mode when the SCCorEn mode bit is asserted. Whenever the processor reads the secondary cache data array in correction mode, the data is sent through a data corrector.

If a correctable error is detected, in-line correction is automatically made without affecting latency. The processor informs the external agent that a correctable error was detected and corrected by asserting SysCorErr* for one SysClk cycle.

If an uncorrectable error is detected, the secondary cache unit posts a Cache Error exception and initializes the D and SIdx fields in the local CacheErr register (see Chapter 14, CacheErr Register (27), for more information).

In correction mode, secondary-to-primary cache refill latency is increased by two PClk cycles. Multiple processors, operating in a lock-step fashion, remain synchronized in the presence of secondary cache data array correctable errors.

Table 9-5 presents the ECC matrix for the secondary cache data array.

Table 9-5

ECC Matrix for Secondary Cache Data Array

Data Array in Noncorrection Mode

When the SCCorEn mode bit is negated, the secondary cache operates in noncorrection mode. Whenever the processor reads the secondary cache data array in noncorrection mode, it checks for even parity on SCDataChk(9). If a parity error is detected, it is assumed that a correctable error has occurred, and the secondary cache block is again read through a data corrector. During this re-read, the processor checks the SCDataChk(8:0) bus for the proper ECC.

If a correctable error is detected, correction is automatically performed in-line. To inform the external agent that a correctable error had been detected and corrected, the processor asserts SysCorErr* for one SysClk cycle.

If an uncorrectable error is detected, the secondary cache unit posts a Cache Error exception and initializes the D and SIdx fields in the local CacheErr register.

Secondary cache data array correctable errors are monitored with Performance Counter 0.

Tag Array

The 26-bit-wide secondary cache tag array is protected by a 7-bit-wide ECC.
Table 9-6 presents the ECC matrix for the secondary cache tag array.

Table 9-6 ECC Matrix for Secondary Cache Tag Array

Whenever the processor reads the secondary cache tag array, it checks the SCTagChk(6:0) bus for the proper ECC. If a correctable error is detected, correction is automatically performed in-line, without affecting latency. The processor asserts SysCorErr* for one SysClk cycle to inform the external agent that a correctable error has been detected and corrected. If an uncorrectable error is detected, the secondary cache unit posts a Cache Error exception and initializes the TA and SIdx fields in the local CacheErr register. The processor asserts SysUncErr* for one SysClk cycle to inform the external agent that an uncorrectable tag error has been detected.

Whenever the processor writes the secondary cache tag array, it drives the proper ECC on the SCTagChk(6:0) bus.

Generated with CERN WebMaker